Power gridding scheme

ABSTRACT

An electrical device includes electrical contact pads, a supply voltage bus and an interconnection circuit. The electrical contact pads receive a supply voltage, and the bus is electrically connected to the electrical contact pads. For each electrical contact pad, the interconnection circuit forms a redundant connection between the bus and the electrical contact pad. The electrical device may include a passivation layer that includes windows to establish electrical contact between the electrical contact pads and the supply voltage bus. This window may be elongated in a path that is generally aligned with the path along which the supply voltage bus extends.

This application is a divisional of U.S. Pat. No. 6,930,379, grantedAug. 16, 2005, which is a divisional of U.S. patent application Ser. No.10/022,700, filed on Oct. 30, 2001

BACKGROUND

The invention generally relates to a power gridding scheme.

Microprocessors are being fabricated with increasingly higher speeds anddevice density. As a result, the power that is consumed by amicroprocessor continues to increase from one generation to the next.This increase in power usage, in turn, may present several challenges.

For example, the microprocessor has a finite number of external contacts(positive and negative supply voltage contacts, for example) tocommunicate power to the microprocessor. For example, these externalcontacts may be solder bumps that are part of a ball and grid package, apackage in which the solder bumps are arranged in a rectangular grid, orarray. In this array, the distances between adjacent solder bumpstypically decreases from one generation microprocessor to the next in anattempt to increase the number of solder bumps that are available tocommunicate power. However, the increase in bump density does not trackthe corresponding increase in the speed and scaling of devices in themicroprocessor. As a result, there is a net reduction in the number ofsolder bumps for power per device in the microprocessor. Thus, the netresult of the increased power density for these solder bumps is that thecurrent densities of some solder bumps may be large enough to possiblycause premature failure of these solder bumps due to the process ofelectromigration (EM).

Thus, there is a continuing need for an arrangement that addresses oneor more of the problems that are stated above.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a partial schematic diagram of an integrated circuit packagedepicting an arrangement of solder bumps according to an embodiment ofthe invention.

FIG. 2 is a cross-sectional view of the package taken along line 2-2 ofFIG. 1.

FIG. 3 is an exploded perspective view of a portion of the packageaccording to an embodiment of the invention.

FIG. 4 is a top view of an interconnection layer of FIG. 3 according toan embodiment of the invention.

FIG. 5 is a cross-sectional view of a semiconductor package according toan embodiment of the invention.

FIG. 6 is a top view of an integrated circuit die according to anembodiment of the invention.

FIG. 7 is a schematic diagram depicting electrical connections betweenbuses and solder bumps according to an embodiment of the invention.

FIGS. 8, 9 and 10 are exploded perspective views of portions ofsemiconductor packages according to different embodiments of theinvention.

FIG. 11 is a cross-sectional view of a portion of a semiconductorpackage according to an embodiment of the invention.

DETAILED DESCRIPTION

Referring to FIG. 1, an integrated circuit package (a microprocessor, asan example) in accordance with an embodiment of the invention includessolder bumps 22 that are located on the outside of the package 10 toform external contacts. In this manner, the package 10 may be a ballgrid package, and the solder bumps 22 may be part of a grid, or array.The solder bumps 22 form contacts for communicating power and signals toand from circuitry of the integrated circuit package 10. As an example,some of the solder bumps 22 may designated to communicate positive andnegative supply voltages to the integrated circuit package 10.

More particularly, FIG. 1 depicts, as examples, specific solder bumps 22a, 22 b and 22 c (for example) that may be used to communicate power tovarious circuitry of the integrated circuit package 10. For thisexample, the solder bumps 22 a, 22 b and 22 c may all communicate thesame positive power supply voltage. The solder bumps 22 a, 22 b and 22 cmay be electrically connected to different internal power, or supplyvoltage, buses 17 of the integrated circuit package 10. In this manner,the solder bumps 22 a and 22 b may be electrically connected to onepositive supply voltage bus 17 a of the integrated circuit package 10,and the solder bump 22 c may be electrically connected to anotherpositive supply voltage bus 17 b of the integrated circuit package 10.

Although the positive supply voltage buses 17 are described below inconnection with the solder bumps 22 a, 22 b, and 22 c, it is understoodthat the same principles apply for other supply voltage buses, such as anegative supply voltage bus 18, for example.

To establish both an electrical and mechanical connection between aparticular solder bump 22 and circuitry inside the integrated circuitpackage 10, a window may be formed in a passivation layer of thesemiconductor die that is encased in the package 10. This passivationlayer forms an outer insulating layer of the die 11 and is locatedbetween the closest internal metal layer of the package 10 and thesolder bumps 22. As a more specific example, referring also to FIG. 2,the integrated circuit package 10 may include a passivation layer 16that generally covers an upper metal layer 62 (a metal six layer, as anexample) of the die 11. The metal layer 62 is exposed for contact withthe solder bumps 22 at several locations at which contact windows areformed in the passivation layer 16.

One of these windows 15 is depicted in FIG. 2. As shown, the window 15exposes a solder bump metal contact pad 66 that is part of the uppermetal layer 62. Thus, the associated solder bump 22 a extends throughthe window 15 to bond to the metal pad 66. This metal pad 66, in turn,is electrically connected to the supply voltage bus 17 a, and thus, thecontact of the solder bump 22 a to the metal pad 66 electricallyconnects the solder bump 22 a to the bus 17 a. As an example of theinterconnection between the metal pad 66 and the bus 17 a, the pad 66may be connected to a metal pad 70 of a lower metal layer 64 by way of avia 67, and this metal pad 70 may be connected to the bus 17 by way ofanother via 71.

The size of the window 15 limits the current carrying capability of thesolder bump 22, as the size of the window 15 defines the area of thesolder bump 22 that contacts the solder bump contact pad 66. Forpurposes of increasing the extent of contact between the solder bump 22and the contact pad 66, in accordance with an embodiment of theinvention, the window 15 is elongated. This elongation permits morecontact area between solder bump 22 and its associated contact pad 66.Thus, selected windows of the integrated circuit package 10 may beelongated for purposes of increasing the current carrying capabilitiesof solder bumps 22 that communicate positive and negative supplyvoltages.

As a more specific example, referring back to FIG. 1, in someembodiments of the invention, the window 15 may be a substantiallyrectangular pad, a pad that is elongated such that the longest dimensionof the window 15 is aligned with the bus 17 that lies underneath thatwindow 15 and is electrically connected to the solder bump 22 thatextends through the window 15. Thus, the major axis of the rectangularwindow 15 is aligned with and located directly above the bus 17 thatextends immediately below the window 15.

In contrast to the elongated shape of the window 15, a window 14 of theprior art, also depicted in FIG. 1 for purposes of comparison, typicallyis square. In this manner, in conventional integrated circuits, the sizeof the square window is limited by the dimension (of the square window14) that is transverse to the bus 17. In contrast, unlike conventionalarrangements, in the integrated circuit 10, although the transversedirection governs the width of the window 15, the length of the window15 is elongated along the bus 17 in a direction to permit more contactbetween the associated solder bump 22 and contact pad 66.

As a more specific example, in some embodiments of the invention, thewindow 15 may have a dimension of approximately 80 by 40 micrometers(μm, or microns), and in other embodiments of the invention may havedimensions of 100 by 150 microns.

It is noted that it is not essential that the window 15 has arectangular shape. In this manner, in other embodiments of theinvention, the window 15 may have different elongated shapes (an ovalshape, for example).

As depicted in FIG. 1, in some embodiments of the invention, the windowsthat are formed in the passivation layer 16 are sized differently. Inthis manner, the windows, in some embodiments of the invention, areselectively sized, in that larger windows are formed for use with somesolder bumps 22 and smaller windows are formed for use with other solderbumps 22. Such an arrangement permits larger windows to be formed forsolder bumps 22 that carry relatively high levels of currents, therebyincreasing the current carrying capabilities of these solder bumps 22;and permits smaller windows to be formed for solder bumps 22 that do notcarry such high levels of current.

As an example of this selective sizing, FIG. 1 depicts the rectangularwindows 15 that are relatively large and are used to increase thecurrent carrying capabilities of solder bumps 22 a and 22 b, as comparedto hexagonal windows 11 that are used by solder bumps 22 d and 22 e. Thehexagonal window 11 is smaller than the window 15 in that the window 11exposes less area of the upper metal layer for contact with theassociated solder bump 22 than the window 15. Thus, the solder bumps 22d and 22 e may be associated with lower currents than the solder bumps22 a and 22 b, for example, and the sizes of their associated windowsreflect this lower current load.

In some embodiments of the invention, as an example of this selectivesizing, some of the windows may be approximately square and havedimensions of approximately 40 by 40 microns; and other larger windows(sized to impart a higher current capability to their associated solderbumps 22) may have dimensions of approximately 80 by 40 microns. Asanother example, in other embodiments of the invention, some of thewindows may be approximately square and have dimensions of approximately100 by 100 microns; and other larger windows (sized to impart a highercurrent capability to their associated solder bumps 22) may havedimensions of approximately 100 by 150 microns. Other variations, sizedifferences and shapes of the windows are contemplated and are withinthe scope of the appended claims.

FIG. 3 depicts another embodiment 200 for the integrated circuitpackage. In this embodiment, the package 10 includes different featuresto increase the current carrying capability of the solder bumps 22. Inthis arrangement, the integrated circuit 10 includes an interconnectionlayer 26 to establish separate and redundant connections between thesolder bumps 22 and the buses 17. For example, in some embodiments ofthe invention, the interconnection layer 26 may form bridges (such asbridges that form a triangle 30, as more clearly depicted in a top viewin FIG. 4) that form redundant connection points 23 between the solderbumps 22 a, 22 b and 22 c. As depicted in FIG. 3, these bridges may bepart of a metal layer that is located between the solder bumps 22 and ametal layer in which the buses 17 are formed. However, in otherembodiments of the invention, the interconnection layer 26 may be formedout of the same metal layer as the buses 17.

FIG. 5 depicts a cross-sectional view of the integrated circuit 200,depicting the interconnection layer 26 as being part of the upper metallayer 62. More particularly, FIG. 5 depicts a portion 208 of the metallayer 62 that forms redundant connections between solder bumps 22 (twosolder bumps 22 being depicted in FIG. 5). In this manner, each solderbump 22 is also connected to the bus 17 that is formed in the lowerlevel metal layer 65. The integrated circuit 200 may have additionalmetal layers that are disposed between the metal layers 62 and 65, suchas a metal layer 64 that is depicted in FIG. 5. In this manner, themetal layer 64 may include metal pads 212 that are connected to themetal portion 208 through vias 210, and the metal pads 212 may beconnected to the bus 17 through other vias 214.

Referring to FIG. 7, the electrical path between a solder bump 22 for asupply voltage and the corresponding bus 17 may be electricallyrepresented by a resistor 100. However, unlike conditional arrangements,the interconnection layer 26 forms redundant connections (depicted bythe electrical connections 102 between the solder bumps 22), therebyeffectively shorting the solder bumps 22 together near the top of thedie to form a lower resistance between each solder bump 22 and itsassociated bus 17.

Although the interconnection layer 26 has been described above inconnection with an integrated circuit package that includes solder bumps22, other arrangements are possible. For example, FIG. 6 depicts a topsurface of a die 40 that includes bond pads 44 for communicating supplyvoltage to and from the die 40. The interconnection layer may be formed,for example, by metal lines 50, or bonding wire, that connects variousbond pads 44 together. For example, the bond pads denoted by thereference numeral “44 b” are connected together via the conductivetraces 50. Other arrangements are possible.

FIG. 8 depicts an integrated circuit package 400 in which theinterconnection layer 26 is formed from conductive traces 150, 152 and154, all of which lie in the same metal layer. Vertical vias 160 formconnections between the traces 150, 152 and 154 and the associated buses17.

FIG. 9 depicts an integrated circuit package 450 in which theinterconnection layer 26 is formed in the same metal layer as the buses17. For example, in some embodiments of the invention, theinterconnection layer 26 may be formed by a conductive trace 120 thatconnects two of the buses 17 together, and another conductive trace 122that connects the other bus 17 to the two connected buses. Otherarrangements are possible.

FIG. 10 depicts another integrated circuit package 500. In the package500, the interconnection layer 26 contains circuitry other thanhard-wired conductive traces. In this manner, in some embodiments of theinvention, the interconnection layer 26 may include switches, such asmetal-oxide-semiconductor field-effect-transistors (MOSFETs) 500, thathave their drain-source paths coupled between various solder bumps 22 toselectively form connection points 23 near the solder bumps 22. Thus,due to this arrangement, the MOSFETs 500 may be selectively closed tocouple groups of the solder bumps 22 together. This arrangement may havevarious advantages, such as permitting grouping of the solder bumps 22after fabrication of a particular integrated circuit. In this manner, itmay be determined that certain solder bumps 22 require higher currentdensities than other solder bumps 22. Thus, the solder bumps 22 thatrequire higher densities are connected together to effectively impart ahigher current carrying capability to each of these bumps 22.

Other embodiments are within the scope of the following claims. Forexample, FIG. 11 depicts an arrangement in which an extra metal layer533 (a metal seven layer, for example) is created on top of thepassivation layer 16 (i.e., on the opposite side of the passivationlayer 16 from the other metal layers) for purposes of forming part orall of the interconnection layer 26. In this manner, the metal for themetal layer 533 may be deposited on top of the passivation layer 16.Next, a mask is used to form an etching pattern for purposes ofpermitting subsequent etching to remove metal from the metal layer 533while leaving conductive traces (the trace 534 depicted in FIG. 11, asan example) to selectively form connections between the solder bumps 22.As depicted in FIG. 11, in an example, two solder bumps 22 f and 22 gare connected together by a conductive trace 534 of the metal layer 533.The solder bumps 22 f and 22 g extend through respective windows tocontact respective metal pads 540 of the next lower metal layer 62.Other variations are possible.

While the present invention has been described with respect to a limitednumber of embodiments, those skilled in the art will appreciate numerousmodifications and variations therefrom. It is intended that the appendedclaims cover all such modifications and variations as fall within thetrue spirit and scope of this present invention.

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 9. An electrical devicecomprising: electrical contact pads to receive a supply voltage; a powerbus electrically connected to the electrical contact pads; and aninterconnection circuit to, for each electrical contact pad, form aredundant connection between the bus and the electrical contact pad. 10.(canceled)
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 25. An electrical device comprising: electrical contactpads to receive a supply voltage; a power bus electrically connected tothe electrical contact pads; and an interconnection circuit to, for eachelectrical contact pad, form a redundant connection between the bus andthe electrical contact pad, wherein the electrical device comprises asemiconductor device comprising having multiple process layers, and theinterconnection circuit is formed in the same process layer as the powerbus.
 26. The electrical device of claim 25, wherein the electricaldevice comprises a microprocessor.
 27. The electrical device of claim25, wherein the electrical contact pads comprise solder bumps.
 28. Theelectrical device of claim 25, wherein the electrical contact padscomprise bond pads.
 29. A method usable with a semiconductor device,comprising: electrical connecting external contacts of a semiconductordevice to internal buses of the semiconductor device, establishingredundant connections between the buses and the external contacts;forming the buses in a first process layer; and forming the redundantconnections in the same first process layer.
 30. The electrical deviceof claim 29, wherein the semiconductor device comprises amicroprocessor.
 31. The electrical device of claim 29, wherein theexternal contacts comprise solder bumps.
 32. The electrical device ofclaim 29, wherein the electrical contact pads comprise bond pads.